The present invention relates generally to the field of non-volatile memory and more particularly to methods and apparatus for isolating defective blocks of memory in a non-volatile memory system.
The use of memory has been increasing due to rapid growth of storage needs in the information and entertainment fields and due to the decreasing size and cost of memory. One type of memory widely used is non-volatile semiconductor memory which retains its stored information even when power is removed. There are a wide variety of non-volatile erasable programmable memories. One widely used type of non-volatile memory is flash memory. A typical commercial form of flash memory utilizes electrically erasable programmable read only memory (EEPROM) devices composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. The storage cells are partitioned internally into independent blocks, each of which forms a set of storage locations which are erasable in a single operation. Each block is the smallest unit which can be erased in a single operation.
When a flash memory device is manufactured, manufacturing defects are normally identified by the manufacturer by in factory testing. In general, as long as a flash memory includes less than a certain number of defective or unusable physical blocks, the flash memory may be sold. In order to increase yield, the manufacturer may include a number of redundant or spare blocks to be used to replace defective blocks. If the number of defective blocks exceeds the number of spare blocks the device is typically discarded. Conventionally, defective blocks at the factory are identified by a test system which tests each device separately and stores the address of defective blocks in test system memory creating a list of defective blocks.
Typically, the test system process for identifying defective blocks begins with providing power to the memory device to be tested and then all blocks of the memory are scanned to identify defective blocks. As the defective blocks are identified, a list of the addresses of the defective blocks is created in the memory of the test system. Once the testing of the device is completed, the defective blocks are marked as defective to permit preventing the defective blocks from being used. In a common approach, the defective blocks or selected pages of the defective block are each individually written (programmed) with all zeros. Other defect marking indicia may also be used. Subsequently, when the memory device is powered up for use, the memory blocks are scanned and the addresses of the marked blocks (e.g., blocks with all zeros stored) are used to create a list of defective blocks. This list is stored in temporary storage on the memory device and used to isolate the defective blocks so that they are not used.
This testing process results in each tested memory device being individually programmed with a defective block indicia such as all zeros. Since testing is typically performed on large numbers (e.g., a wafer of many die) of memory devices, the testing is inefficient unless many devices can be tested in parallel. Parallel testing of many memory devices at a time using the conventional test process requires a complex test system with large amounts memory to store the lists of defective blocks and then program the blocks. Further, this conventional approach limits the number of blocks that can be defective on a usable memory because the memory device cannot usually be sold if the number of defective blocks exceeds the spare blocks manufactured on the memory device.
Therefore, there is a need for a method and apparatus which enables identification and isolation of defective memory blocks which does not require storage of defective block lists in the test fixture. In addition, there is a need for a method and apparatus to enable more efficient marking of defective blocks which does not require that each defective block be separately programmed to indicate it is defective.